1 04-02-030d peel tm 22cv8 peel? 22cv8 -5/-7/-10/-25 cmos programmable electrically erasable logic device n n n n high speed, low power - speeds ranging from 5ns to 25ns - less power than quarter-power pals and gals n n n n cmos electrically erasable technology - superior factory testing - reprogrammable in plastic package - reduces retrofit and development costs n n n n development/programmer support - third party software and programmers - ict place development software and - pds-3 programmer n n n n architectural flexibility - 24-pin version of popular peel18cv8 - 74 product term x 44 input array - up to 22 inputs and 8 i/o pins - up to 12 configurations per macrocell - synchronous preset, asynchronous clear - individual product-term driven oe controls n n n n application versatility - replaces random logic - super-sets standard plds (pal, gal, epld) - enhanced architecture fits more logic than ordinary plds - 24-pin dip/soic/tssop, 28-pin plcc the peel22cv8 is a programmable electrically erasable logic (peel) device providing an architecture-enhanced low power alternative to ordinary plds such as the gal20v8. the peel22cv8 is available in 24-pin dip/ soic/tssop and 28-pin plcc packages (see figure 1) with speeds ranging from 5ns to 25ns (the 5ns speed grade is available only in the plcc package). the low power consumption of this device (10ma typical for the 25ns speed grade) makes it ideal for power-sensitive applica- tions such as portable communication equipment, comput- ers and peripherals. ee-reprogrammability provides the convenience of instant reprogramming for development and a reusable production inventory minimizing the impact of programming changes or errors. ee-reprogrammability also improves factory testability, thus ensuring the highest quality possible. the peel22cv8 architecture allows it to replace over 20 standard 24-pin plds (pal, gal, epld, etc.), often at less than half of the power of a quarter power gal. the device also provides additional architectural fea- tures so more logic can be put into every design. develop- ment and programming support for the peel22cv8 is provided by popular third-party programmers and develop- ment soft-ware. ict also offers free place development software and a low-cost development system (pds-3). dip plcc soic 1 2 3 4 5 6 7 8 i/clk i i i i i i i vcc i i/o i/o i/o i/o i/o i/o 24 23 22 21 20 19 18 17 9 10 i i i/o i/o 16 15 11 12 i gnd i i 14 13 tssop figure 1. pin configurations figure 2. block diagram commercial general description features
2 04-02-030d peel tm 22cv8 figure 3. peel 22cv8 logic array diagram (pin numbers are for dip and soic packages, plcc pin numbers are shown in parentheses.) i i i i i i i 2 (3) 23 (27) i/clk 0 0 64 72 7 8 16 24 32 40 48 56 15 23 31 39 47 55 63 73 15 20 25 30 35 40 43 10 5 synchronous preset (to all macrocells) asynchronous clear (to all macrocells) 1 (2) 3 (4) 4 (5) 5 (6) 6 (7) 7 (9) 8 (10) i 9 (11) i 10 (12) i 11 (13) i 14 (17) 15 (18) 16 (19) 17 (20) i 13 (16) macro cell i/o 21 (25) macro cell i/o 20 (24) macro cell i/o 19 (23) macro cell i/o 18 (21) macro cell i/o macro cell i/o macro cell i/o macro cell i/o i 22 (26)
3 04-02-030d peel tm 22cv8 function description the peel22cv8 implements logic functions as sum-of products expressions in a programmable-and/fixed-or logic array. user-defined functions are created by program- ming the connections of in-put signals into the array. user- configurable output structures in the form of i/o macrocells further in-crease logic flexibility. architecture overview the peel22cv8 architecture is illustrated in the block dia- gram of figure 2. fourteen dedicated inputs and eight i/os provide up to 22 inputs and 8 outputs for creation of logic functions. at the core of the device is a programmable elec- trically-erasable and array which drives a fixed or array. with this structure the peel22cv8 can implement up to 8 sum-of-products logic expressions. associated with each of the 8 or functions is an i/o mac- rocell which can be independently programmed to one of 12 different configurations. the programmable macrocells allow each i/o to create sequential or combinatorial logic functions of active-high or active-low polarity, while provid- ing three different feedback paths into the and array. and/or logic array the programmable and array of the peel22cv8 (shown in figure 3) is formed by input lines intersecting product terms. the input lines and product terms are used as fol- lows: n n n n 44 input lines: 28 input lines carry the true and complement of the signals applied to the 14 input pins 16 additional lines carry the true and complement values of feedback or input signals from the 8 i/os n n n n 74 product terms: 64 product terms (arranged in groups of 8) used to form sum-of-products functions 8 output enable terms (one for each i/o) 1 global synchronous preset term 1 global asynchronous clear term at each input-line/product-term intersection, there is an eeprom memory cell which determines whether or not there is a logical connection at that intersection. each prod- uct term is essentially a 44-input and gate. a product term which is connected to both the true and complement of an input signal will always be false and thus will not affect the or function that it drives. when all the connections on a product term are opened, a dont care state exists and that term will always be true. when programming the peel22cv8, the device program- mer first performs a bulk erase to remove the previous pat- tern. the erase cycle opens every logical connection in the array. the device is configured to perform the user-defined function by programming selected connections in the and array. (note that peel device programmers automatically program at least one pair of complementary inputs on unused product terms so that they will have no effect on the output function.) programmable i/o macrocell the unique twelve-configuration output macrocell provides complete control over the architecture of each output. the ability to configure each output independently permits users to tailor the configuration of the peel22cv8 to the precise requirements of their designs. macrocell architecture each i/o macrocell, as shown in figure 4, consists of a d- type flip-flop and two signal-select multiplexers. the config- uration of each macrocell is determined by the four eeprom bits controlling these multiplexers. these bits determine: output polarity, output type (registered or non- registered) and input/feedback path (bi-directional i/o, combinatorial feedback or register feedback). refer to table 1 for details. equivalent circuits for the twelve macrocell configurations are illustrated in figure 5. in addition to emulating the four pal-type output structures (configurations 3, 4, 9 and 10) the macrocell provides eight additional configurations. when creating a peel device design, the desired macro- cell configuration generally is specified explicitly in the design file. when the design is assembled or compiled, the macrocell configuration bits are defined in the last lines of the jedec programming file. output type the signal from the or array can be fed directly to the out- put pin (combinatorial function) or clocked into the d-type flip-flop (registered function). the d-type flip-flop loads data on the rising edge of the clock and is controlled by the glo- bal preset and clear terms. when the synchronous preset term is satisfied, the q output of the register will be set high at the next rising edge of the clock input. satisfying the asynchronous clear term will set q low, regardless of the clock state. if both terms are satisfied simultaneously, the clear will override the preset. output polarity each macrocell can be configured to implement active-high or active-low logic. programmable polarity eliminates the need for external inverters. output enable the output of each i/o macrocell can be enabled or dis- abled under the control of its associated programmable output enable product term. when the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to the i/o pin. otherwise, the output buffer is driven into the high-impedance state.
4 04-02-030d peel tm 22cv8 under the control of the output enable term, the i/o pin can function as a dedicated input, a dedicated output, or a bi- directional i/o. opening every connection on the output enable term will permanently enable the output buffer and yield a dedicated output. conversely, if at least one com- plementary pair of connections is intact, the enable term will always be logically false and the i/o will function as a dedicated input. input/feedback select the peel22cv8 macrocell also provides control over the feedback path. the input/feedback signal associated with each i/o macrocell may be obtained from three different locations: from the i/o pin (bi-directional i/o), directly from the q output of the flip-flop (registered feedback) or directly from the or gate (combinatorial feedback). bi-directional i/o the input/feedback signal is taken from the i/o pin when using the pin as a dedicated input or as a bi-directional i/o. (note that it is possible to create a registered output func- tion with bi-directional i/o.) combinatorial feedback the signal-select multiplexer gives the macrocell the ability to feedback the output of the or gate, bypassing the out- put buffer, regardless of whether the output function is reg- istered or combinatorial. this feature allows the creation of asynchronous latches, even when the output must be dis- abled. (refer to configurations 5, 6, 7 and 8 in figure 5.) registered feedback feedback also can be taken from the register, regardless of whether the output function is to be combinatorial or regis- tered. when implementing combinatorial output functions, registered feedback allows internal registering of states without giving up the use of the external output. programmable input and i/o pin pull-ups the input and i/o pins on this device feature programmable pull-up circuitry which can be globally enabled or disabled during design entry. (in the ict place software, for exam- ple, the pull-ups can be activated by selecting the design...auxiliary menu, the default is no pull-ups.) enabling the pull-ups causes input and i/o pins to be pulled high through nominally 100k ohms. design security the peel22cv8 provides a special eeprom security bit that prevents unauthorized reading or copying of designs programmed into the device. the security bit is set by the pld programmer, either at the conclusion of the program- ming cycle or as a separate step after the device has been programmed. once the security bit is set it is impossible to verify (read) or program the peel until the entire device has first been erased with the bulk-erase function. figure 4. block diagram of the peel22cv8 i/o macrocell
5 04-02-030d peel tm 22cv8 figure 5. equivalent circuits for the twelve configurations of the peel22cv8 i/o macrocell table 1. peel 22cv8 macrocell configuration bits configuration input/feedback select output select # a b c d 1 1 1 1 1 bi-directional i/o register active low 2 0 1 1 1 active high 3 1 0 1 1 combinatorial active low 4 0 0 1 1 active high 5 1 1 1 0 combinatorial feedback register active low 6 0 1 1 0 active high 7 1 0 1 0 combinatorial active low 8 0 0 1 0 active high 9 1 1 0 0 register feedback register active low 10 0 1 0 0 active high 11 1 0 0 0 combinatorial active low 12 0 0 0 0 active high
6 04-02-030d peel tm 22cv8 table 1. absolute maximum ratings symbol parameter conditions ratings unit v cc supply voltage relative to ground -0.5 to + 7.0 v v i , v o voltage applied to any pin 2 relative to ground 1 -0.5 to v cc + 0.6 v i o output current per pin (i ol , i oh )25ma t st storage temperature -65 to + 150 c t lt lead temperature soldering 10 seconds +300 c table 2. operating ranges symbol parameter conditions min max unit v cc supply voltage commercial 4.75 5.25 v t a ambient temperature commercial 0 +70 c t r clock rise time see note 3 20 ns t f clock fall time see note 3 20 ns t rvcc v cc rise time see note 3 250 ms table 3. d.c. electrical characteristics over the recommended operating conditions symbol parameter conditions min max unit v oh output high voltage v cc = min, i oh = -4.0ma 2.4 v v ohc output high voltage - cmos 13 v cc = min, i oh = -10a v cc - 0.3 v v ol output low voltage - ttl v cc = min, i ol = 16ma 0.5 v v olc output low voltage - cmos 13 v cc = min, i oh = -10a 0.15 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage -0.3 0.8 v i il input i/o leakage current low v cc = max, v in = gnd, i/o = high z -10 a i ilp input, i/o leakage current low-input and i/o pull-ups enabled v cc = max, v in = gnd, i/o = high z -100 a i ih input i/o leakage current low v cc = max, v in = v cc 10 a i sc output short circuit current v cc = 5v, vo = 0.5v 9 , t a = 25c -30 -150 ma i cc 10 v cc current (see cr-1 for typical i cc ) v in = 0v or 3v f = 25mhz all outputs disabled 4 -5 75 (typ) 110 ma -7 60 (typ) 110 -10 60 (typ) 110 -25 10 (typ) 15 c in 7 input capacitance t a = 25c, v cc = 5.0v @ f = 1 mhz 6pf c out 7 output capacitance 12 pf this device has been designed and tested for the recommended operating conditions. proper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may cause per- manent damage.
7 04-02-030d peel tm 22cv8 table 4. a.c. electrical characteristics symbol parameter -5 -7 -10 -25 unit min max min max min max min max t pd input 5 to non-registered output 5 7.5 10 25 ns t oe input 5 to output enable 6 5 7.5 10 20 ns t od input 5 to output disable 6 5 7.5 10 20 ns t co1 clock to output 4 7 7 12 ns t co2 clock to comb. output delay via internal registered feedback 7.5 10 12 30 ns t cf clock to feedback 2.5 3.5 4 10 ns t sc input 5 or feedback setup to clock 3.5 5 5 15 ns t hc input 5 hold after clock 0000ns t cl , t ch clock low time, clock high time 8 33.5512ns t cp min clock period ext (t sc + t co1 ) 7.5 12 12 27 ns f max1 internal feedback (1 tsc + t cf ) 12 166.7 117.6 111 40 mhz f max2 external feedback (1/t cp ) 12 133 83.3 83.3 37 mhz f max3 no feedback (1/t cl + t ch ) 12 166.7 142.8 100 41.6 mhz t aw asynchronous reset pulse width 5 7.5 10 25 ns t ap input 5 to asynchronous reset 5 7.5 10 25 ns t ar asynch. reset recovery time 5 7.5 10 25 ns t reset power-on reset time for registers in clear state 55105s inputs, i/o, registered feedback, synchronous preset clock asynchronous reset registered outputs combinatorial outputs 1. minimum dc input is -0.5v; however, inputs may undershoot to -2.0v for periods less than 20ns. 2. v i and v o are not specified for program/verify operation. 3. test points for clock and v cc in tr, tf are referenced at 10% and 90% levels. 4. i/o pins are 0v or 3v. 5. input refers to an input pin signal. 6. .t oe is measured from input transition to v ref 0.1v, t od is measured from input transition to v oh - 0.1v or v ol + 0.1v; v ref = v l . see test loads in section 5 of ict data book. 7. capacitances are tested on a sample basis. 8. test conditions assume: signal transition times of 3ns or less form the 10% and 90% points, timing reference levels of 1.5v (unless otherwise specified). 9. test one output at a time for a duration of less than 1 sec. 10. i cc for a typical application: this parameter is tested with the device programmed as an 10-bit counter. 11. peel device test loads are specified in section 6 of the data book. 12. parameters are not 100% tested. specifications are based on initial characterization and are tested after any design or process modifica- tion which may affect operational frequency. 13. available only for 22cv8-25 . switching waveforms notes: over the operating limit 8,11
8 04-02-030d peel tm 22cv8 table 5. ordering information
peel22cv8j-5* 5ns c j28 peel22cv8p-7* 7.5ns c p24 PEEL22CV8J-7* j28 peel22cv8s-7* s24 peel22cv8p-10* 10ns c p24 peel22cv8j-10* j28 peel22cv8s-10* s24 peel22cv8p-15 15ns c p24 peel22cv8j-15 j28 peel22cv8s-15 s24 peel22cv8p-25 25ns c p24 peel22cv8j-25 j28 peel22cv8s-25 s24 part number device peel 22cv8p-25 package p = plastic 300mil dip j = plastic (j) leaded chip carrier (plcc) s = soic t = tssop temperature range and power options (blank) = commercial 0 to 70c speed -5 = 5ns tpd -7 = 7.5ns tpd -10 = 10ns tpd -15 = 15ns tpd -25 = 25ns tpd suffix *contact ict for availability of this device in -5, -7, -10 speed grades, as well as all speed grades in tssop packages.
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